The present invention relates to an inverse assembler that provides code only information during inverse assembly to reduce the number of data acquisition channels used by the logic analyzer and, the present invention converts a logical address into the necessary trigger commands used by a logic analyzer to trigger an associated physical address in memory.
Typically, microprocessor-based systems are programmed in a high level programming language using programming code, such as, for example, C. The programming code of the high level programming language is converted using a compiler into binary code that corresponds to executable steps performed by the microprocessor. When debugging a software application, the programmer can disassemble the binary code using an inverse assembler which converts the binary code into machine code instructions. These machine code instructions relate to mnemonics that indicate the operations that the microprocessor is performing while executing the software application.
During conventional disassembly, a logic analyzer probes the memory bus connecting the microprocessor to the memory. The memory bus, typically, includes an address bus, a data bus and a status bus. Once the logic analyzer probes the memory bus, the logic analyzer can be triggered to acquire the binary code. The inverse assembler translates the binary code into a machine code instruction (mnemonic). The programmer can then determine the operations that the microprocessor is performing by viewing the actual machine code instructions translated by the conventional inverse assembler, and therefore, the programmer obtains valuable insight to assist in debugging any problems associated with the software application.
As mentioned above, the conventional inverse assembler relies on a logic analyzer to probe and acquire data from the memory busses. The logic analyzer includes data acquisition cards that have a finite number of channels used to obtain the binary code from the memory busses. The logic analyzer and data acquisition cards are expensive. Some programmers desire an inexpensive alternative to these expensive logic analyzers to obtain machine code information relating to a software application. In addition, other programmers desire to have the finite number of channels on the data acquisition card available to probe other information during debugging.
Therefore, a need exists for an inverse assembler that reduces the number of data acquisition channels used by the logic analyzer during disassembly, and a need exists for an inverse assembler that reduces costs associated with probing the memory busses, in particular, the data bus, using the logic analyzer.
During debugging of the memory busses, the programmer must setup the trigger specification for the logic analyzer correctly. Usually, the programmer wishes to view data at a particular address on the memory bus. In order to view this data, the programmer must determine a logical address assigned to the binary code and translate that logical address to a physical address in memory. In earlier conventional microprocessors, the translation of logical address to physical address was not difficult. Typically, the logical address was the same as the physical address. However, with newer microprocessor and memory controllers, the translation between the logical address into the physical address is no longer standard and has become increasingly complex. Unlike earlier conventional microprocessors and memory controllers that used the logical address as the physical address, current memory controllers such as for example, SDRAM and DRAM on-chip memory controllers, typically, provide non-logical addresses as physical addresses in memory. With these newer microprocessors, the programmer must have intimate knowledge of the microprocessor in order to properly trigger the physical address. If the programmer does not have this knowledge, the programmer does not have the ability to obtain the proper conversion between the logical address and the physical address. Therefore, the incorrect binary code can be acquired by the logic analyzer and input to the inverse assembler. Therefore, the machine code instructions are incorrect and debugging the software application becomes futile.
Thus, a need exists for an apparatus and method that understands the microprocessor and memory controller and converts a logical address into a physical address for the programmer and sets up the logic analyzer to trigger the physical address such that the programmer does not require an intimate knowledge of the memory mapping techniques used by the microprocessor.
The present invention includes an inverse assembler that provides code only information and, therefore, reduces the number of logic analyzer channels used during inverse assembly. In addition, the present invention also provides an inverse assembler whose requirements are less expensive than conventional inverse assemblers that probe all memory busses during inverse assembly. Also, the present invention provides a trigger tool that understands the microprocessor and the memory controller to convert a logical address into trigger commands used by the logic analyzer to trigger an associated physical address in memory for the programmer without requiring the programmer to have intimate knowledge of the memory mapping techniques of the microprocessor.
The present invention provides a method for inverse assembly of a software application. During compiling of programming code, a memory image file is generated. During inverse assembly in the present invention, a logical address is determined that indicates a location of a binary code in memory. The memory image file is searched for the logical address. The binary code is acquired from the memory image file at the logical address. The binary code corresponds to only machine code instructions performed during execution of the software application. The binary code is converted into machine code instructions so as to perform the inverse assembly of the compiled programming code for the software application.
In another aspect of the present invention, a method for acquiring binary code during inverse assembly of compiled programming code for a software application is provided. The present invention uses a converter (trigger tool) to trigger a physical address in a memory bus via a logic analyzer. A triggered logical address in the compiled programming code is provided. The triggered logical address is input into the converter. Trigger commands are provided that convert the triggered logical address and step up the logic analyzer to trigger the associated physical address where the binary code is stored in memory. The trigger commands are supplied to the logic analyzer and the memory bus is triggered using the logic analyzer. The binary code is acquired from the memory bus and the binary code is converted into machine code instruction or a data value so as to perform inverse assembly on the software application.